Technical Lead : Memory Design

Responsibilities:

As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA.

Required Skills and Experience :

Understanding of computer architecture and concepts.

Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis and Monte Carlo Simulations.

Good experience in design verification: Sense amplifier analysis, self-time analysis and marginality analysis.

Understanding of high speed/low power CMOS circuit design, clocking scheme, Static and complex logic circuits.

Understanding of Power versus Performance versus Area trade-offs in typical CMOS design.

Strong knowledge of physical implementation impact on circuit performance.

Good understanding of high-performance and low power circuit designs with exposure to FinFet technologies, bitcell stability analysis

Proven experience as the designated responsible individual for a memory design, leading a small team of designer.

Expected to have good interpersonal skills.

Circuit Design: Design and develop digital circuits for memory blocks like SRAM, register files, and caches.

Simulation and Verification: Perform simulations and verification to ensure functionality and optimize for power, performance, area, timing, and yield.

Minimum 7 Yrs of experience in SRAM / memory design Margin, Char and its related quality checks.

Nice To Have Skills and Experience :

Some Experience of working on Cadence or Synopsys flows.

Experience with Circuit Simulation and Optimization of standard cells.