Senior Technical Lead – Post-Silicon Validation & RTOS SDK

Job Overview

Join the RISC-V Revolution! We`re looking for a senior technical leader to drive both post-silicon validation (AVV) and RTOS SDK development for our next-gen RISC-V-based automotive real-time MCUs. You`ll lead the software team responsible for validating first silicon and developing production-grade SDKs that enable real-world applications like EV control, ADAS, and safety-critical domain computing.

Key Responsibilities

• Team Leadership: Build and lead a 10+ member cross-functional embedded software team. Define execution plans, schedules, and quality metrics across SDK and AVV. Mentor team members; provide guidance on technical challenges and project delivery.
• RTOS SDK Development: Own the architecture and delivery of the RTOS SDK, including BSPs, HALs, low-level drivers, and middleware. Ensure modular, scalable SDK structure supporting AUTOSAR and non-AUTOSAR stacks. Deliver example applications and customer reference packages. Drive code reuse across internal validation and customer deliverables.
• Post-Silicon AVV: Define and execute software-centric AVV strategy for post-silicon validation. Validate key subsystemsADCs, PWMs, Ethernet, timers, watchdogs, CAN, LIN, FlexRay, etc. Lead first-silicon bring-up, in-depth debugging, and regression testing. Implement AVV use cases covering functional, real-time, and safety behaviours. Ensure ASIL-D level functional safety validation, using SIL, HIL, and fault injection. Build automation infrastructure supporting lab validation and CI pipelines.
• Cross-Functional Collaboration: Work closely with system architects, hardware, and safety teams. Provide feedback to hardware design and influence next-gen RISC-V CPU and SoC features. Interact with internal and external stakeholders to align roadmaps and execution.
• Customer & Ecosystem Engagement: Collaborate with OEM, Tier-1 customers on integration, onboarding, and SDK adoption. Contribute to the RISC-V open-source ecosystem, including toolchain, RTOS, and libraries
  
  

Qualifications

• Bachelor`s or Master`s in Embedded Systems, Computer Engineering, or Electrical Engineering.
• 10+ years of experience in embedded software development and/or post-silicon validation, with at least 2+ years in a leadership role.
• Proven expertise in RTOS (e.g., FreeRTOS, Zephyr, AUTOSAR OS), device drivers, and real-time control systems.
• Hands-on experience with bring-up, experience with debugging tools (OpenOCD, Segger J-Link, Lauterbach), and validation of complex SoC, MCU peripherals and safety features.
• Strong knowledge of automotive communication protocolsCAN, LIN, FlexRay, UART, SPI, I2C.
• Solid scripting and automation experience (Python, Bash, etc.) and familiarity with CI/CD tools. 5+ years of practical experience in embedded software development, debug.
  
  

Additional Qualifications

• Experience with ASIL-D safety-compliant software, ISO 26262 software V-model, and generating safety work products.
• Prior experience delivering SDKs for Tier-1s or OEMs, especially in motor control, powertrain, or chassis applications.
• Knowledge of bootloaders, firmware update mechanisms, and secure embedded software practices.
• Familiarity with RISC-V ISA. Knowledge of different Instruction Set Architectures (e.g. x86_64, ARM64)
  
  

Benefits

At MIPS, you`ll be a member of a fast-growing team of technologists that are creating the industry`s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure – you`ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry`s most experienced CPU engineers. An unlimited growth path – with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting-edge applications with industry-leading customers. At MIPS we provide meaningful benefits programs and products to our associates and their families.