Technical Lead Engineer-RTL

• Noida, Bangalore and Hyderabad

Role :

• The RTL Lead Engineer performs detailed block design from system requirements and evolving specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with Synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power, and area goals

Desired Skills:

• Develop HW architecture from specification documents.
• Owning responsibilities include writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL.
• Develop and execute low power design intent (UPF/CPF).
• Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc
• Knowledge of low-speed bus protocols (AMBA/OCP) and high-speed serial protocols (PCIe/USB/Ethernet) will used at various stages of the design.
• Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures.
• Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional break.
• Take ownership of tasks and drive tasks to closure
• Must have gone through at least 3 tape-out of a large, high speed designs

Experience : 6 to 9 Years