Chennai, Tamil Nadu, India
Information Technology
Full-Time
Happiest Minds Technologies
Overview
Verification of RTL designs for FPGA -Block/subsystem/chip/system level functional verification
-Implement verification environment in SV using UVM methodology according to the architecture specification
-Development and execution of test cases -Report test results and assist in RTL debug using simulation
-3 - 6 years of hands-on experience of verification in customer projects
-Bachelors/Masters in Electronics Engineering
-Strong communication skills mandatory
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